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Principal Front End Design Methodology Engineer
Mountain View, CA
Job Description
OverviewMicrosoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Front End Design Methodology Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. As the Front End Methodology Engineer, you will be responsible for developing and maintaining the Register Transfer Level (RTL) design flows and methodologies for our cutting edge chip productions. Throughout the program you will be interacting with various teams, including architecture, front end design, verification, design for testing( DFT) and physical design to ensure quality, performance and efficiency of RTL code and tools. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
ResponsibilitiesResponsibilitiesArchitect and implement workflows using industry-standard tools and best practices that aid in System on a Chip (SOC) assembly including RTL handoff between Intellectual Property (IPs)/subsystems/SOC/DFT teams, hierarchy manipulation and feedthrough methodologies, constraint and waiver promotion, specification to design collateral flows etc.Provide guidance and training to the RTL design team on usage of the flows and methodologiesCollaborate with RTL design, verification, DFT and Physical design teams to resolve any issues related to RTL code, tools or flowsEvaluate new tools, technologies and standards for RTL design and propose improvements and enhancementsDocument and maintain the RTL design flows and methodologies
ResponsibilitiesResponsibilitiesArchitect and implement workflows using industry-standard tools and best practices that aid in System on a Chip (SOC) assembly including RTL handoff between Intellectual Property (IPs)/subsystems/SOC/DFT teams, hierarchy manipulation and feedthrough methodologies, constraint and waiver promotion, specification to design collateral flows etc.Provide guidance and training to the RTL design team on usage of the flows and methodologiesCollaborate with RTL design, verification, DFT and Physical design teams to resolve any issues related to RTL code, tools or flowsEvaluate new tools, technologies and standards for RTL design and propose improvements and enhancementsDocument and maintain the RTL design flows and methodologies
Job Summary
Company
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Experience
Open
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